High voltage generator incorporated in an integrated circuit

ABSTRACT

A high voltage generator (GHT) incorporated in an integrated circuit (IC) and comprising a charge pump ( 1 ) whose input voltage is the supply voltage (V DD ) of the integrated circuit (IC) and which is clocked by direct clock signals (Φ) and complemented clock signals ({overscore (Φ)}), characterised in that it comprises means ( 5 ) for re-injecting a fraction (V IN ) of the voltage from said charge pump (V HV ) into the input ( 6 ) to which said supply voltage (V DD ) is applied.

[0001] The present invention relates to a high voltage generatorincorporated in an integrated circuit.

[0002] The invention relates more particularly to a high voltagegenerator for reading and writing data in an EEPROM.

[0003] High voltage generators of the above type, also known as chargepumps, generally comprise a series of voltage multipliers consisting ofcapacitors and diodes (or transistors connected as diodes) that multiplyby a given factor an input voltage that is typically the supply voltageof the integrated circuit. A high voltage generator of the above kind isdescribed in a paper by J. F. Dickson published on 3 Jun. 1976 in IEEEJournal Of Solid State Circuits, Vol. SC. 11, No.3, pages 374-378,entitled “On-chip high voltage generation in NMOS integrated circuitsusing an improved voltage multiplier circuit”, for example. Thedisclosure of that paper is hereby incorporated by reference into thepresent description.

[0004] Thus if the charge pump comprises 14 stages, for example, it ispossible to generate a voltage up to ten times a given supply voltage,for example 2 volts, at the input of the charge pump.

[0005] However, this kind of high voltage generator has a number ofdrawbacks, as it requires a relatively large circuit structure, forwhich space must be reserved on the integrated circuit.

[0006] Moreover, integrating this kind of integrated circuit intoportable objects such as telephones, cards or even laptop computers doesnot lead to optimum battery life conditions in respect of therequirements of the object itself. One major concern in this field isreducing power consumption and using the lowest possible circuit supplyvoltage, in particular to extend the service life of the power supplymeans.

[0007] An object of the present invention is to alleviate the drawbacksof the prior art referred to above and in particular to provide a highvoltage generator of the generic type indicated that either generates ahigh voltage using a charge pump comprising a much smaller number ofmultiplier stages than was necessary in the prior art or reduces powerconsumption by using a lower circuit supply voltage.

[0008] Thus the invention consists in a high voltage generatorincorporated in an integrated circuit and comprising a charge pump whoseinput voltage is the supply voltage of the integrated circuit and whichis clocked by direct clock signals and complemented clock signals,characterised in that it comprises means for re-injecting a fraction ofthe voltage from said charge pump at the input to which said supplyvoltage is applied.

[0009] Thanks to these features, and compared to prior art high voltagegenerators, it is possible either to obtain a high voltage at the outputof the generator with a small number of multiplier stages or to apply amuch lower voltage to the input of the charge pump to obtain acomparable high voltage.

[0010] The generator according to the invention may also have one ormore of the following features:

[0011] said re-injection means comprise an adiabatic reducer;

[0012] the re-injection coefficient of said re-injection means is in therange from 0 to 1;

[0013] the re-injection coefficient is equal to 0.5;

[0014] said adiabatic reducer comprises two capacitors and switchingmeans for connecting said capacitors alternately in series to saidvoltage from the charge pump and in parallel to supply said voltagefraction;

[0015] said capacitors have the same capacitance;

[0016] the working frequency of said charge pump is equal to the clockfrequency of said switching means.

[0017] The invention further consists in an integrated circuitcomprising a high voltage generator as defined hereinabove andcharacterised in that it comprises an EEPROM supplied by said highvoltage generator.

[0018] Other features and advantages of the present invention willbecome apparent in the course of the following description, which isgiven by way of example only and with reference to the appendeddrawings, in which:

[0019]FIG. 1 is a simplified block diagram of a high voltage generatoraccording to the invention;

[0020]FIG. 2 is a theoretical circuit diagram of an adiabatic reducerused in the high voltage generator according to the invention;

[0021]FIG. 3 is a theoretical circuit diagram of a variant of theadiabatic reducer; and

[0022]FIG. 4 is an explanatory diagram showing the output voltage of thegenerator as a function of its output current, the diagram comprising inparticular two straight load lines.

[0023]FIG. 1 is a simplified block diagram of a high-tension generatorGHT according to the invention. It is incorporated into an integratedcircuit IC and, in this example, supplies power to an EEPROM. Of course,the integrated circuit IC may include other functional units that arenot shown.

[0024] The high voltage generator GHT comprises a voltage multiplierunit 1 formed of a charge pump that is known in the art and theoperation of which is clocked by two-phase clock signals, namely adirect signal D and a complemented signal D, which are applied toterminals 2 and 3, respectively, of the unit 1. These clock signals maybe derived from a main clock (not shown) of the integrated circuit IC,for example. Note that the clock signals used may equally benon-interlaced four-phase signals.

[0025] The multiplier unit 1 receives the voltages V_(DD) and V_(SS) ofthe integrated circuit IC. It has an output terminal 4 at which therequired high voltage V_(HV) is available. The multiplier unit 1 maycomprise n multiplier stages, the number of stages being selected as afunction of the required output voltage V_(HV). The multiplier unit maybe of any type known in the art, for example that depicted in FIG. 5 ofthe paper previously cited.

[0026] According to the invention, the high voltage generator alsocomprises means 5 for re-injecting a fraction V_(in) of its outputvoltage at an input terminal 6 of the unit 1. If the unit 1 is based onthe circuit depicted in FIG. 5 of the paper previously cited, theterminal 6 may be connected to the line of that circuit to which thevoltage V_(DD) is applied.

[0027] In the embodiment shown, the re-injection means 5 take the formof an adiabatic reducer, the term “adiabatic” in the present contextmeaning that the reducer does not dissipate energy. In other words, theproduct of its input voltage by its input current is equal to theproduct of its output voltage by its output current.

[0028] The adiabatic reducer 5 has an input terminal 7 to which isapplied the output voltage V_(HV) available at the output terminal 4. Italso has an output terminal 8 at which appears the voltage V_(in) thatis applied to the input terminal 6 of the multiplier unit 1.

[0029] The adiabatic reducer has a reduction coefficient ρ such that thehigh open circuit voltage V_(HV) produced at the output of the generatoris defined by the equation: $V_{HV} = \frac{V_{HV0}}{1 - \rho}$

[0030] in which V_(HV0) represents the high open circuit voltage of themultiplier unit 1 in the absence of the adiabatic reducer 5 and thecoefficient ρ may be from 0 to 1. Under these conditions, the voltageV_(HV) could, at least theoretically, be from V_(HV0) to ∞. However, themaximum output voltage that can be obtained is obviously limited byconstruction contingencies of the integrated circuit IC and inparticular by the breakdown voltages of its components.

[0031]FIG. 2 is a theoretical circuit diagram of an adiabatic reducerthat may be used in the high voltage generator GHT according to theinvention. This reducer is based on the switched capacitor principle. Itcomprises a series circuit comprising, from the input terminal 7 toground, the drain-source path of a transistor T1, a first capacitor C1,the drain-source path of a transistor T2, and a second capacitor C2. Thedrain-source path of a third transistor T3 is connected between the nodecommon to the transistor T1 and the capacitor C1 and the node common tothe transistor T2 and the capacitor C2. The node common to the thirdtransistor T3 and the capacitor C2 forms the output terminal 8 of theadiabatic reducer. The node common to the capacitor C1 and thetransistor T2 is grounded via the drain-source path of a transistor T4.

[0032] The reduction coefficient p is fixed by the chosen circuit, inparticular as a function of the number of switched capacitors and theirrespective capacitance values. It is preferably made equal to 0.5, as inthe situation of two capacitors of equal capacitance, it beingunderstood that a circuit using this value is convenient to implementand confers a high overall multiplication coefficient on the highvoltage generator.

[0033] The transistors T1 to T4 form switching means and their gates aredriven by respective clock signals G1 to G4 whose duration anddistribution in time are chosen to achieve the following mode ofoperation. In a first phase the two capacitors C1 and C2 are charged inseries by the input voltage V_(HV) and in a second phase the twocapacitors are connected in parallel to produce the output voltageV_(IN) of the reducer 5, which is half the voltage V_(HV), so thatp=0.5. The two phases are repeated periodically and the repetitionfrequency may be equal to the pumping frequency of the multiplier unit 1(for example a few hundreds of kHz).

[0034]FIG. 3 shows a variant of the adiabatic reducer 5. This circuitcomprises the transistors T1, T3 and T4 from the FIG. 2 theoreticalcircuit diagram connected to the capacitors C1 and C2 in the same way.The transistor T2 is preferably replaced by a diode D1 if the circuittechnology allows the use of floating diodes (for example polysilicondiodes).

[0035] The drain and the gate of the transistor T1 are connectedtogether via a diode D2, and a capacitor C3 is connected to the gate ofthe transistor T1 in order to apply to it a complemented clock signal{overscore (H)}, the direct version H of which is received by the gateof the transistor T4 and the gate of the transistor T3, the clock signalbeing applied in this case via a capacitor C4. A diode D3 connects thisgate to the terminal 8.

[0036] In the FIG. 3 embodiment, the function of the diodes D2 and D3 isto bias the respective transistors T1 and T3 so that they are turned offwhen the clock pulses are absent.

[0037] The high voltage generator according to the invention uses fewermultiplier stages in the charge pump 1 to obtain a high voltage from agiven supply voltage than would be required in a high voltage generatorwith no re-injection means 5. For example, a charge pump with fourteenstages could multiply the open circuit voltage of 2 V to approximately20 V, whereas with the high voltage generator according to theinvention, in which the coefficient ρ=0.5, just seven booster stages inthe charge pump 1 suffice.

[0038] Conversely, if the high voltage generator according to theinvention comprises the same number of multiplier stages in the chargepump 1 as a prior art embodiment, it is possible to obtain a highvoltage comparable to that obtained in the prior art embodiment from alower supply voltage. In the above example, and considering the sameopen circuit voltage, the same output high voltage of 20 V may beobtained with a supply voltage of only approximately 1.5 V. Obviouslythis may be very important in applications where only a low supplyvoltage is available (as in electronic timepieces, for example).

[0039]FIG. 4 is a graph showing the operation of the high voltagegenerator according to the invention with the output high voltage V_(HV)plotted on the ordinate axis and the load current i_(LO) plotted on theabscissa axis. The figure shows a first straight load line DC1 of thecharge pump of the unit 1 in the absence of re-injection (ρ=0) and astraight load line DC2 for the situation with re-injection (ρ=0.5).

[0040] Note that the open circuit high voltage, i.e. the voltage in theabsence of a load current (i_(LO)=0), is V₀ without re-injection and 2V₀with re-injection.

[0041] Similarly, the short circuit current halved, which corresponds toquadrupling the internal resistance.

[0042] A beneficial region of the generator may be defined as thecross-hatched region corresponding to an output voltage of the generatorwith a reduction coefficient of 0.5 that is higher than the outputvoltage of the multiplier with a zero reduction coefficient. This regionis delimited by the intersection point 1. For a given working frequency,the beneficial region covers currents less than 20% of the short-circuitcurrent, defined as the current supplied by the generator if the outputis grounded. It is nevertheless possible to increase the current rangein this region by increasing the frequency of the clock signals, as thetwo are related.

[0043] Note that the description refers to the use of MOS transistors,in particular for implementing the adiabatic reducer, but that producinga similar reducer with bipolar transistors may be envisaged.

[0044] It is to be understood that the description is given by way ofexample only and that other embodiments, in particular of the adiabaticreducer, may fall within the scope of the present invention.

1. A high voltage generator incorporated in an integrated circuit and comprising a charge pump whose input voltage is a supply voltage of the integrated circuit and which is clocked by direct clock signals and complemented clock signals further comipising means for re-injecting a fraction of a voltage from said charge pump at the input to which said supply voltage is applied.
 2. The generator according to claim 1, wherein said re-injection means comprise an adiabatic reducer.
 3. The generator according to claim 2, wherein the re-injection coefficient of said re-injection means is in the range from 0 to
 1. 4. The generator according to claim 3, wherein the re-injection coefficient is equal to 0.5.
 5. The generator according to claim 2, wherein said adiabatic reducer comprises two capacitors and switching means for connecting said capacitors alternately in series to said voltage from the charge pump and in parallel to supply said voltage fraction.
 6. The generator according to claim 5, wherein said capacitors have the same capacitance.
 7. The generator according to claim 5, wherein the working frequency of said charge pump is equal to the clock frequency of said switching means.
 8. An integrated circuit comprising a high voltage generator according to claim 1, wherein it comprises an EEPROM powered by said high voltage generator. 